The present invention relates generally to a novel computer processing architecture, and more particularly to a processing core in which one register in a register file stores the program counter and another register in the register file always stores a zero value, making address calculations and program jumps and branches quicker and more efficient.
Computer architecture designers are constantly trying to increase the speed and efficiency of computer processors. For example, computer architecture designers have attempted to increase processing speeds by increasing clock speeds and attempting latency hiding techniques, such as data pre-fetching and cache memories. In addition, other techniques, such as instruction-level parallelism using very long instruction word (VLIW) designs, and embedded-DRAM have been attempted. However, one of the best methods of improving speed and efficiency in computer processors is to improve the efficiency of the instruction set, and in particular, decreasing the number of instructions required to perform a particular function.
In the prior art computer architectures, the program counter typically is stored in a special register apart from the register file used by the processing pipeline. After instructions have been executed, the program counter typically is updated, so that the computer processor properly progresses through program execution. With these prior art architectures, branch and jump instructions typically are individual instructions within an instruction set. Thus, to perform branch and jump functions, the branch or jump program location first is calculated, and then the jump instruction is executed. As one skilled in the art will appreciate, to perform a proper jump or branch function, as many as 6 or 7 instructions may be executed. Thus, it is desirable to have a processing architecture, which can perform jumps and branches more efficiently.
Similarly, in the prior art processing architectures, retrieving data from a memory location can require as many as 6 to 10 program instructions. For example, address calculation values must be retrieved, the memory address must be calculated from the retrieved calculation values, and a load or fetch from memory must be executed. In addition, if data fetch errors occur, the data fetch process typically is repeated. Thus, data fetches from memory can be a big processing bottleneck, especially if fetch errors occur. Therefore, it would be advantageous to simplify the data load or data fetch process.